1. Field of the Invention
The present invention relates generally to computer aided methods and tools for designing, simulating, and verifying integrated circuit (IC) designs. More specifically, the present invention relates to an efficient and accurate process of characterizing a plurality of instances of a memory compiler circuit.
2. Description of the Prior Art
The design of very large scale integrated (VLSI) circuits using computer aided design (CAD) systems is a very time-consuming and computationally intensive process. As the complexity of VLSI circuit design has increased, a trend has developed wherein VLSI circuit designers incorporate basic circuit building blocks into circuit designs so that the designers no longer start from scratch in designing a chip. This design approach is commonly referred to as an intellectual property (IP) based design approach, and the basic circuit building blocks are referred to as IP blocks.
In accordance with system on a chip (SOC) technology, a variety of circuit building blocks are incorporated onto a single integrated chip, each of the building blocks performing a specific function of an electronic system. The IP building blocks required for a system chip include embedded memory devices such as SRAM, DRAM, ROM, EPROM, and EEPROM type memory devices. It is common for a single SOC to require between 50 and 100 memory devices. Often, more than 50% of the layout area of a system chip is devoted to embedded memory. Because reusability is a key factor in SOC methodology, system chip designers typically reuse a particular embedded memory design throughout a system chip with minor differences between each instance of the memory design such as variations in the size of the memory array of each instance. The selection of a memory instance is typically determined by an IC designer based on system design requirements and the availability of silicon real estate on the system chip. Different configurations of a memory circuit design are also provided. Such configurations include dual port memory and single port memory.
Design layouts for memory circuit IP building blocks are currently available to IC designers from vendors who provide memory layout databases for a memory compiler, or circuit design, different types of memory circuits. A vendor's memory compiler team may generate thousands of memory instances for each type of memory circuit. Memory compiler tools are used to generate a layout and a netlist for each memory circuit design. Components of memory compiler software used by a memory compiler team typically include a circuit design tool, a layout design tool, and a characterization tool.
IC designers require a timing model including a plurality of characterized timing parameters for each memory instance that the IC designer intends to incorporate into a system chip as embedded memory. Important timing parameters include setup time, hold time, memory access time, minimum pulse high and low time, and other I/O pin characteristics. Memory compilers and IC designers are both interested in characterizing and optimizing timing characteristics associated with a memory design.
Memory compiler teams need to generate a timing model by characterizing each of the timing parameters for each memory instance. A timing model for a memory instance may be determined to a certain degree of accuracy by simulating the memory instance. However, simulation of all of the timing characteristics of a memory instance is a very time consuming and computationally intensive process. Because there may be thousands of memory instances for each memory compiler, it is difficult to generate a white box timing model, that is a timing model based on actual simulation results, for each one of the memory instances. A "black box timing model" for a particular instance of a memory design may be estimated using equations and look up tables determined based on timing models determined for other instances of the memory design having a predetermined relationship with the particular memory instance as further explained below. Typically, a memory compiler vendor will generate a white box timing model for "corner" instances of a memory design such as a first instance having a smallest size memory array that is likely to be used by an IC designer, and a second instance having a largest size memory array that is likely to be used in practice. Black box timing models for memory instances having array sizes ranging between those of the first and second characterized instances are typically determined by interpolation techniques or by equations providing estimated timing characteristics. A vendor's memory compiler typically provides the lookup table and/or equations to IC designers for determining the timing characteristics associated with each memory instance. However, the accuracy of typical prior art black box timing models is not consistent. Furthermore, curve fitting is difficult for multi-dimensional variables.
FIG. 1 shows a generalized circuit block diagram of a memory circuit at 10 that may be used for modeling an instance of embedded memory in a system chip. The memory circuit 10 includes: an address decoder 12 having a plurality of address signal inputs 14 for receiving address signals; an array 16 of memory cells 18 arranged in rows and columns, each cell 18 being communicatively coupled with the address decoder 12 via an associated one of a plurality of word lines 20, which are typically designated by the memory compiler team using convenient names such as WORD_LINE.sub.-- 0, WORD_LINE.sub.-- 1, . . . WORD_LINE_N, for addressing rows of the array; a sense amplifier 24 responsive to column select address information provided by the address decoder 12, and being coupled with each of the cells 18 of the array via an associated one of a plurality of lines 26; a data input buffer 30 having a plurality of ports 32 each being communicatively coupled with one of the bit lines 26, and having at least one input port 34 for receiving a data input signal designated D.sub.IN from a source (not shown) that may be provided by another device on the IC chip or provided by an external device via an I/O pin of the chip; and a data output buffer 40 communicatively coupled with the sense amplifier 24 as shown by a line 42 and having at least one output 44 for providing a data output signal designated D.sub.OUT to processing circuitry (not shown) on the IC chip or to external processing circuitry via an I/O pin of the system chip.
FIG. 2 shows a flow diagram at 70 illustrating a prior art semi-manual process of characterizing timing parameters for a memory instance of a particular memory circuit design which may be modeled generally by the memory circuit 10 (FIG. 1). The process begins with step 72 in which a memory instance layout data base is generated by a memory compiler team. Note that the process 70 of characterizing timing parameters may be performed by either a memory compiler team, or by an IC designer in which case step 72 may include receiving the memory instance layout database from a vendor. The memory instance comprises a layout database that defines a particular instance memory circuit of a compiler having an array of cells including a plurality of M rows and a plurality of N columns, each cell being defined by a core cell. In step 47, an IC designer performs a partial layout extraction sub-process including manual estimation and segmenting to generate a netlist. Layout extraction generally refers to a process of converting a layout data base into an extracted electric circuit representation including circuit components such as transistors, resistors, capacitors. etc. The extracted electric circuit representation may then be used for simulating the circuit in order to characterize timing parameters. Note that a memory instance layout database may include millions of geometric objects, and therefore a full scale layout extraction process is computationally intensive, and very time consuming. In order to reduce the time and processing power required for the layout extraction process, a manual estimation and segmenting process is traditionally performed by the test engineer to generate a partially extracted and manually estimated netlist.
From step 47, a semi-manual circuit segmenting sub-process 76 is executed on the circuit level using the partially extracted and manually estimated netlist generated in step 74. The circuit segmenting sub-process includes: a step 80 of partitioning the circuit represented by the partially extracted netlist (assumed to be modeled by the memory circuit 10 of FIG. 1) into blocks including at least portion of the address decoder 12 (FIG. 1), the array 16 of memory cells 18, sense amplifier 24, data input buffer 30, and data output buffer 40; and a step 82 of manually generating a critical path circuit netlist for each of the blocks.
The semi-manual circuit segmenting sub-process 76 is described with reference back to FIG. 1. Consider that each of the word lines 20 (FIG. 1) is connected to each of a row of 128 of the memory cells 18. It is generally sufficient to determine timing parameters associated with the four corner memory cells 48 of the array. As an example, in characterizing the access time for the cell 48 that is furthest from the address decoder 12 and connected thereto via WORD_LINE.sub.-- 0, it is necessary to consider a signal path extending from an associated one of the address inputs 14 designated A.sub.0 to an associated one of the outputs 44 via the particular memory cell 48. This signal path is segmented into a plurality of signal path segments including: a first segment 50 extending through the address decoder 12 from the address input A.sub.0 to WORD_LINE.sub.-- 0; a second segment 52 extending via the WORD_LINE.sub.-- 0 from address decoder 12 to the particular memory cell 48; a third segment 54 extending via an associated one of the bit lines 26 from the particular memory cell 48 to the sense amplifier 24; a fourth segment 56 extending through the sense amplifier 24 from the associated one of the bit lines 26 to the data output buffer 40; and a fifth segment 58 extending through the data output buffer 40 to the associated output 44. A sixth segment 59 is shown extending through the data input buffer 30 from one of the input ports 34 to an associated one of the bit lines 26. A test engineer performing the semi-manual circuit segmenting sub-process 76 analyzes the partially extracted netlist generated in step 74 to determine each of the segments 50, 52, 54, 56, and 58 (FIG. 1). This is a very time consuming and error-prone process.
Typically, characteristics of the selected critical paths are only estimated because the electrical coupling effects of other circuit paths on the selected paths are either completely ignored or approximated in order to minimize the time and processing power required to ultimately generate the timing characteristics associated with the selected path. For example, input signals applied to the address inputs A.sub.1, A.sub.2, A.sub.3, . . . , A.sub.N effect the circuit performance of the first segment 50 connected to the first address input A.sub.0 of the address decoder 12 (FIG. 1) through electrical coupling effects. However, the coupling effects of signals applied to address pins A, A.sub.2, A.sub.3, . . . , A.sub.N are typically ignored in modeling the circuit performance of the first segment 50 because it is too time consuming to consider the RC coupling effects of each of these such circuits. This results in decreased accuracy in the timing model for the selected critical path.
From step 82, the process proceeds to step 84 in which the test engineer adjusts the critical path circuit netlist generated in steps 80 and 82 as described above by parameterized loading of selected ones of the segments of the critical paths. As an example, characteristics of the second signal path segment 52 (FIG. 1) traversing WORD_LINE.sub.-- 0 between the address decoder and the memory cell 48 are typically estimated in accordance with a method wherein the remaining memory cells connected to WORD_LINE.sub.-- 0 are modeled by parameterized loading values. Each of the memory cells connected to WORD_LINE.sub.-- 0 causes a side loading of the second signal path segment 52. Parameterized loading values for the signal path segment 52 are typically estimated for each of a plurality of selected groups 60 of the memory cells connected to WORD_LINE.sub.-- 0. Likewise, parameterized loading values for the third path segment 54 are typically estimated for each of a plurality of selected groups 62 of the memory cells connected to the associated one of the bit lines 26.
Having been adjusted by parameterized loadings in step 84, the manually generated critical path circuit netlist is simulated in step 86 using a standard commercially available circuit simulation program such as HSPICE.TM.. In step 88, timing results are generated for each of the critical paths. Results must be generated for a plurality of parameters including access time, setup time, hold time, and pulse width. The circuit netlist created as a result of the semi-manually performed steps 74, 80, 82, and 84 described above is a reduced circuit netlist and therefore the time and processing power required to execute the simulation step 86 is reduced. However, the performance of steps 74 through 84 is very time consuming.
In accordance with the conventional circuit segmenting sub-process 76, the RC coupling between two segments is ignored. For example, the total delay through a plurality of interconnected segments is determined by determining a sum of the timing delays through each of the paths, such as adding the decoder path delay to the memory array delay to the sense amp delay. This results in incomplete or inaccurate results because the coupling effects are not accurately accounted for.
Simulation of the reduced circuit netlist yields a timing model for the selected critical paths that is not very accurate and prone to errors due to the above described manual estimations performed in steps 74, 80, 82, and 84. Another disadvantage of the conventional semi-manual process 70 of characterizing timing parameters for a memory instance is that it is very time consuming to perform each of the steps of the process. It is impractical or unfeasible to characterize the timing models for all of the memory instances because there may be thousands of memory instances and it is far too time consuming to characterize each one. Therefore, white box timing models are typically only determined for a group of 10 or 20 corner instances of an embedded memory circuit design, and black box timing models for additional memory instances are usually determined by interpolation techniques or by equations based on the characterizations of the corner instances.
FIG. 3 shows an interpolation diagram at 90 generally illustrating a memory instance timing parameter interpolation diagram. A white box model for a first set of timing characteristics is determined for a first memory instance 92, and a white box model for a second set of timing characteristics is determined for a second memory instance 94. A black box timing model may be subsequently determined by interpolation for a third memory instance 96 that is assumed to have timing characteristics within a range defined by the first and second memory instances 92 and 94. The diagram 90 generally illustrates a black box timing model which may be actually implemented using either look up tables or equations.
Problems with the parameterized approach of the prior art characterization methods include the difficulty of scaling, and non-linear correlation in the resulting timing model. The actual variations in RC effects from one array size and aspect ratio to another are not linear as assumed in prior art characterization methods. Also, the parameterized loading, described above, cannot be assumed to increase linearly as array size increases, and without regard for differences in aspect ratio.
Another problem associated with the segmenting approach of conventional characterization methods is that timing parameters such as setup, hold time, and minimum pulse width are only estimated. In order to increase performance of a memory circuit, these timing parameters should be optimized. In accordance with conventional characterization methods, these timing parameters are typically estimated very conservatively in order to achieve accurate performance criteria without optimal performance.
As described above, in accordance with the prior art memory characterization tools, many functions must be performed manually or at least semi-manually. In accordance with prior art memory characterization methods, the manual segmenting of circuits piece by piece is very time consuming and cumbersome and must be repeated many times for each embedded memory instance having a different size such as a different word count or a different bit count. Also, there is a danger of making an overly simplified assumption that secondary effects such as RC coupling are ignored in the prior art memory characterization methods.
What is needed is an automatic memory characterization system that provides improved accuracy in determining timing characteristics of a circuit.
What is also needed is an automatic memory characterization system that provides the ability to characterize timing parameters of a large number of memory instances of a memory compiler in a relatively short period of time with minimal effort by a user of the system.